The present invention relates to a dynamic semiconductor storage device and a method of reading and writing operations thereof, and more particularly to a dynamic random access memory (DRAM) and a method of reading and writing operations thereof.
Hitherto, portable devices or the like, which are required to feature low power consumption, have been using SRAM (Static Random Access Memory). However, the SRAMs are being increasingly replaced by DRAMs featuring lower bit unit cost in response to the demand for larger capacities with the trend toward higher performance and more versatility of portable devices.
Meanwhile, it is necessary for DRAMs to perform refreshing operations at predetermined intervals to retain data even in a standby mode. The power consumed for the refreshing operations amounts to about 80 percent to about 90 percent of total power consumed in the standby mode, and it is therefore required to be considerably reduced.
A typical DRAM adopts a common sense amplifier system, in which a single sense amplifier is shared by a pair of bit lines so as to reduce a layout area. Furthermore, the DRAM adopts a half-Vdd precharging method in which the pair of bit lines is precharged to a voltage Vdd/2, which is a half of a supply voltage Vdd, so as to reduce power consumption.
Japanese Unexamined Patent Application Publication No. 2001-84767 discloses a DRAM equipped with a sense amplifier that permits fast amplification and fast rewrite without adversely affecting advantages of the half-Vdd precharging method.
Referring to FIG. 4, the DRAM is provided with a top array TA, a bottom array BA, a P-type sense amplifier PSA, an N-type sense amplifiers NSAt and NSAb, an isolator BLIt that disconnect bit lines BLt and /BLt of the top array TA from shared lines SA and /SA, and an isolator BLIb that disconnect bit lines BLb and /BLb of the bottom array BA from shared lines SA and /SA.
The P-type sense amplifier PSA is connected between the shared lines SA and /SA. The sources of P-channel MOS transistors P2 and P3 constituting the P-type sense amplifier PSA are both connected to a Vdd power supply. The N-type sense amplifier NSAt is connected between the bit lines BLt and /BLt, and includes N-channel MOS transistors N7 and N8. The N-type sense amplifier NSAb is connected between the bit lines BLb and /BLb, and includes N-channel MOS transistors N9 and N10.
The reading operation of the DRAM will now be explained with reference to the timing chart shown in FIG. 5.
The bit lines BLt and /BLt are equalized by an equalizing transistor (N-channel MOS transistor) N1 and precharged to Vdd/2 (0.8V in this example) before time t1. The shared lines SA and /SA are equalized by an equalizing transistor (P-channel MOS transistor) P1 and precharged to a predetermined voltage (1.2V in this example).
When a voltage WLt of a word line increases to a step-up voltage (2.6V in this example) at time t1, a potential difference is developed between the bit lines BLt and /BLt.
When a set signal SETt goes to “H” (logical high) level (Vdd=1.6V in this example) at time t2, a drive transistor (N-channel MOS transistor) N11 turns on. This actuates the N-type sense amplifier NSAt, and the voltage of the bit lines BLt or /BLt, whichever is lower (the voltage of the bit line BLt in this example), is pulled down to a ground potential (GND=0V in this example).
When an isolation control signal ISOt rises at time t3, the isolator BLIt turns on. The gate voltages of the N-channel MOS transistors N3 and N4 are boosted to be higher than the supply voltage Vdd by their threshold voltages (2.1V in this example). Hence, the voltages of the bit line BLt and the shared line SA will be the same, and the bit line /BLt and the shared line /SA will be also the same. As a result, a potential difference occurs also between the shared lines SA and /SA.
The P-type sense amplifier PSA constantly remains actuated, so that as soon as the potential difference takes place between the shared lines SA and /SA, the voltage of the shared line SA or /SA, whichever is higher (the voltage of the shared line /SA in this example), is pulled up to the supply voltage Vdd (1.6V in this example).
When a column selection signal CSL goes to the “H” level at time t4, column selection gates (N-channel MOS transistors) N13 and N14 turn on, and data signals on the shared lines SA and /SA are read onto data lines DL and /DL.
The column selection signal CSL returns to “L” (logical low) level at time t5. The voltage WLt of the word line returns to the ground potential at time t6. The set signal SETt returns to the “L” level and the isolation control signal ISOt returns to the ground potential at time t7.
As described above, the DRAM uses a “two-stage sensing method” in which the N-type sense amplifier NSAt starts its operation at time t2, and the P-type sense amplifier PSA starts its operation at time t3. The DRAM, therefore, requires long time for the reading operation.
When the data signals are read from the shared lines SA and /SA into the data lines DL and /DL, the P-type sense amplifier PSA must drive the data lines DL and /DL with heavy load, causing the voltages of the shared line /SA and the bit line /BLt to temporarily drop. To rewrite (or restore) the data signal destructively read out from a memory cell, the voltage WLt of the word line must be dropped after the voltages of the shared line /SA and the bit line /BLt are reset to the supply voltage Vdd. For this reason, the interval between time t5 and time t6 is set to be longer.
The writing operation of the DRAM will now be explained with reference to the timing chart shown in FIG. 6.
The operation before time t2 is the same as that of the aforesaid reading operation. In this example, the N-type sense amplifier NSAt pulls the voltage of the bit line BLt down to the ground potential.
When the column selection signal CSL goes to the “H” level at time t3, the column selection gates N13 and N14 turn on, and the data signals on the data lines DL and /DL are transferred onto the shared lines SA and /SA. In this example, the shared line SA has the supply voltage Vdd, while the shared line /SA has the ground potential. At this point, the isolator BLIt is still off, so that the voltages of the bit lines BLt and /BLt are not equal to the voltages of the shared lines SA and /SA.
When the isolation control signal ISOt rises at time t4, the isolator BLIt turns on. The voltages of the bit lines BLt and /BLt and the shared lines SA and /SA will be the same. In this example, the bit line BLt has the supply voltage Vdd, while the bit line /BLt has the ground potential.
The operation after time t5 is the same as that of the reading operation described above.
In a write mode, the writing operation described above is performed on the selected pair of bit lines; however, the writing operation is not necessarily performed on an adjacent pair of bit lines thereof. On such an adjacent pair of bit lines, a reading operation is performed to restore data signals destructively read from the memory cell. The data signals widely swing on the pair of bit lines on which the writing operation is performed, so that the data signals may be reversed due to the influences of coupling noises in the pair of bit lines on which the reading operation is carried out. In order to reduce the influences, therefore, the isolator BLIt must be turned on after the N-type sense amplifier NSAt sufficiently amplifies the data signals read onto the bit lines. Hence, the interval between time t2 and time t4 is longer.
To write reverse data signals from the read data signals, the data signals sufficiently amplified by the N-type sense amplifier NSAt must be reversed. Thus, the interval between time t4 and time t5 is longer.
Meanwhile, Japanese Unexamined Patent Application Publication No. 2002-298577 discloses a DRAM that has achieved markedly reduced refresh current by reducing all voltages, including a supply voltage. In the DRAM, the number of memory cells connected to a bit line is cut down by half so as to cut down the capacity of the bit line by half in order to secure a sufficient reading potential difference.
In the DRAM shown in FIG. 4, however, the threshold voltages of the transistors P2 and P3 of the P-type sense amplifier PSA are approximately 0.6V, so that the supply voltage Vdd can be reduced only down to approximately 1.0V.
Accordingly, a method is conceivable, in which the supply voltage Vdd remains unchanged, namely, 1.6V, while the gate voltages of the isolators BLIt and BLIb are set to the supply voltage Vdd (1.6V) rather than 2.1V, and the voltage of one of the bit lines, whichever is higher, is clamped. This method makes it possible to significantly reduce power consumption in an array by reducing the internal voltage of the array to approximately 0.8V. However, in the half-Vdd precharging method, the precharge voltage of the bit lines will be approximately 0.4V (=0.8V÷2), so that the gate-drain voltages of transistors N7 to N10 will be low. This leads to significantly slow operations of the N-type sense amplifiers NSAt and NSAb.